1. Technical Field
Various embodiments relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus and an operating method thereof.
2. Related Art
A semiconductor memory apparatus is configured to store input data and output the stored data. At this time, the semiconductor memory apparatus outputs the stored data in response to a clock signal having the same phase as an external clock signal used an external device.
The semiconductor memory apparatus may include a circuit element for generating a delay locked loop (DLL) clock signal to output data at the same phase as the external clock signal.
Referring to FIG. 1, a conventional semiconductor memory apparatus 1 may include a delay unit 10, a phase comparison unit 20, a replica 30, and a fuse unit 40.
The delay unit 10 may be configured to decide a delay time in response to a comparison signal com_s, delay an external clock signal CLK_in by the decided delay time, and output the delayed signal as a DLL clock signal CLK_dll.
The phase comparison unit 20 may be configured to compare the phases of the external clock signal CLK_in and a feedback clock signal CLK_fb and generate the comparison signal com_s.
The replica 30 may be configured to delay the DLL clock signal CLK_dll and generate the feedback clock signal CLK_fb. The replica 30 may have a delay time obtained by modeling an internal delay time of the semiconductor memory apparatus 1.
The fuse unit 40 may be configured to provide a plurality of delay control signals DL_ctrl<0:n> to the replica 30, in order to control the delay time of the replica 30. The fuse unit 40 may include a plurality of fuses (not shown), and generate the plurality of delay control signals DL_ctrl<0:n> depending on the respective fuses are cut or not.
The delay time of the replica 30 may be initially set during the replica 30 is designed. Then, during a test operation, the initially-set delay time may be controlled and corrected through a fuse cutting technique.
However, after the semiconductor memory apparatus is shipped from a manufacturer, the delay time of the replica 30 cannot be controlled. Therefore, when a user uses the semiconductor memory apparatus in a poor environment, the delay time of the replica 30 needs to be controlled again.